🧑🏭 This week we are going back to building a Testing PCB for resonant half bridge topologies, idea that I addressed and developed in one of my previous Newsletters.
At Frenetic, one of our goals is to really integrate Power Electronics, Magnetics design and mass production together in your projects. We’re already doing it with our clients offline, but the ultimate goal is to have everything gathered in a single platform.
🤝 Power Electronics goes hand in hand with Magnetics
From time to time, we get some requests to design entire prototypes, and not just the magnetic components. This is a hard task that can take weeks, even months. In my career, I was mainly responsible for bringing crazy ideas to life, so I can claim a bit of expertise on the matter. Particularly when it comes to debugging hardware… 🫣
🕵️ When I support clients who are designing their magnetic components, I like to investigate the Power Electronics side of things first, and check the client’s specs on Magnetics. I can’t stress enough how important specs are to make sure our design behaves properly under every working condition.
Enough talking, let’s get into today’s topic now!
⚙️ Time to design together!
Back in Newsletter #57, I shared the schematics of the following board, and this week I decided to update them to raise the power level to ~1.5kW, which is about the maximum we should demand for a half-bridge design. That’s not actually written in stone, but if you put the numbers down for rms currents, you’ll quickly see the exponential rise of conduction losses limits the use of the half-bridge above 1.5-2kW.
Figure 1. Altium PCB design
Figure 2. Altium schematics (Half bridge part)
My approach to design is to justify every decision made in the schematics first, and then lay out the PCB. I have circled in Figure 2 some interesting areas that we’re going to explore in this Newsletter.
✅ CN4 is the input connector where a wire from the PSU/PFC is connected supplying 390V-420V. That cable might be like 1m long, so an LC tank will be created from the wire and C1. That’s why we insert L1& R5 to make sure that the L1,C1,R5 tank is damped sufficiently. The cable effect is insignificant now.
✅ C1 placement in the board is significant and we should make sure the distance from QA-drain and QB-source is as short as possible. You should always think of wires in schematics like small inductors (which they are…). High circulating currents move from C1 through the bridge, through Magnetics and back to this decoupling capacitor. The choice of this capacitor to 10uF/film type MKP is just fine for any bridges up to 2-3kW (and maybe even higher).
Figure 3. C1 placement in PCB
✅ Another key point is the distance between QA-source and QB-drain, which also needs to be minimized. The inductance that is forming there is very damaging when it comes to any hard switching conditions, because it will create voltage spikes and high frequency oscillations (like 30, 50, 100MHz) in the rising/falling edge of the pulse. Of course, I don’t plan on using this in hard switched conditions, but let me ask you this:
🤔 Are you sure when you have a bridge set up for ZVS (no matter the topology), that during the first pulses of the train waive (for example burst mode – start up condition) the mosfets will experience ZVS?
The reality is that at least the first pulse will experience some hard switching, because usually the bridge before that was off, so the Coss of the mosfets were charged at Vbus/2 voltage, and hard switching will happen since there is no fly-wheeling action before that (like seen in
🔎 Investigation in detail
Figure 4. Start-up overshoot example
☝️Notice the QB-VDS overshoot in the example of Figure 4 (other project – same issues). From 390V we overshoot to 520V, which is about 33%. That’s why the app notes are recommending you to choose 600-650V class mosfets for 400V bus voltages as safety margin.
I will disclose here that RC damping (220pF + 4.7R in series) was added to each mosfet drain-source to achieve that maximum 33% overshoot, in the expense of a slightly smaller ZVS range in that project I built a couple years ago. Without the filters, I think I was getting overshoots somewhere around 580V, which was close to the mosfet VDS breakdown limit.
Of course, mosfets won’t fail necessarily >600V (IPP60R070CFD7) as they will enter avalanche mode, but given the repeatability of the problem, and the fact that this is not a single-shot pulse problem staying below <600V is the way to ensure reliability and robustness.
🤓 To sum up
That is the level of attention we give to designs that aspire to become products one day. You got a glimpse of some closely guarded secrets that engineers rarely share and usually find out the hard way, if no senior engineer is there to teach…
🤯 I belong to that category myself. Lots of hours spent on a scope, trying to understand why this is overshooting. At what frequency? How can I improve? How can I simulate the parasitic components in LTspice?
📩 I would love for senior engineersto reach out to me replying to this email, correcting me, pointing things out and sharing more secrets for all Frenetic readers!
🔋 We will be taking some time-off in the next few weeks to recharge our batteries in the beaches and mountains. We’ll be back with new and even better content for you all!
✨ Enjoy the summer break, and see you in the next one.
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✨ Take your knowledge of Magnetics components to the next level with the Mag & Mad Conference!
Save the date: September 13-14, 2023 | Madrid, Spain.
🚀 Mark your calendars and get ready to immerse yourself in a world of possibilities at Mag & Mad!
